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mirror of https://github.com/cmur2/python-veml6070.git synced 2025-06-26 12:30:19 +02:00

module: add pylint and fix accordingly

This commit is contained in:
cn
2018-03-13 16:50:25 +01:00
parent 2086f111f2
commit 5466a3ff2d
4 changed files with 564 additions and 16 deletions

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@ -1,3 +1,3 @@
from veml6070 import Veml6070
from veml6070 import INTEGRATIONTIME_1_2T, INTEGRATIONTIME_1T, INTEGRATIONTIME_2T, INTEGRATIONTIME_4T, RSET_240K, RSET_270K, RSET_300K, RSET_600K
from .veml6070 import Veml6070
from .veml6070 import INTEGRATIONTIME_1_2T, INTEGRATIONTIME_1T, INTEGRATIONTIME_2T, INTEGRATIONTIME_4T, RSET_240K, RSET_270K, RSET_300K, RSET_600K

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import smbus
import time
ADDR_L=0x38 # 7bit address of the VEML6070 (write, read)
ADDR_H=0x39 # 7bit address of the VEML6070 (read)
import smbus # pylint: disable=import-error
RSET_240K=240000
RSET_270K=270000
RSET_300K=300000
RSET_600K=600000
ADDR_L = 0x38 # 7bit address of the VEML6070 (write, read)
ADDR_H = 0x39 # 7bit address of the VEML6070 (read)
SHUTDOWN_DISABLE=0x00
SHUTDOWN_ENABLE=0x01
RSET_240K = 240000
RSET_270K = 270000
RSET_300K = 300000
RSET_600K = 600000
INTEGRATIONTIME_1_2T=0x00
INTEGRATIONTIME_1T=0x01
INTEGRATIONTIME_2T=0x02
INTEGRATIONTIME_4T=0x03
SHUTDOWN_DISABLE = 0x00
SHUTDOWN_ENABLE = 0x01
class Veml6070:
INTEGRATIONTIME_1_2T = 0x00
INTEGRATIONTIME_1T = 0x01
INTEGRATIONTIME_2T = 0x02
INTEGRATIONTIME_4T = 0x03
class Veml6070(object):
def __init__(self, i2c_bus=1, sensor_address=ADDR_L, rset=RSET_270K, integration_time=INTEGRATIONTIME_1T):
self.bus = smbus.SMBus(i2c_bus)